1. Field of the Invention
The invention is related to the non-volatile memory controller technology and more particularly to the encoding of the information during the write process and error correction during the read process from such memory.
2. Description of the Related Art
The main challenges of NAND Flash Memory are its higher cost relative to Hard-Disk-Drive storage, slow sequential write time, limited endurance (defined as the maximum number of Program/Erase cycles) and limited high temperature data retention time. These challenges are inter-related: in order to improve cost, one must use higher-density (more bits per cell) Flash, which in turn worsens its endurance and data retention. As an example, SLC (single level charge) Flash is typically rated for 100K or 50K P/E (Program/Erase) cycles and 2-bit per cell MLC (multiple level charge) Flash is typically rated for 10K, 5K or even as few as 3K P/E cycles.
Therefore, there is a need in the art for a method and system that provide for the improved reliability in reading and recovering data from the Flash memories.